1. Technical Field
The present invention relates to an access control apparatus for executing access control when a plurality of masters access a shared memory, and especially to a technology to improve responsiveness to an access request of a master which irregularly makes the access request.
2. Background Art
There is a system in which a memory is shared by a master which needs to access the memory at a constant rate during a predetermined period (hereinafter, referred to as a “real time master” or simply a “master”), and a master which irregularly makes an access request for the memory and hence the occurrence of the access request is difficult to predict (hereinafter, referred to as a “processor”).
Such a system usually includes a circuit for arbitrating between the real time master and the processor in order to prevent a memory access contention therebetween.
Generally, a system will fail unless the real time master makes an access request at a constant rate during a predetermined period. For example, in a system like a television, problems like dropping frames and display of the previous frame can occur.
On the contrary, the system will not fail even if it lacks responsiveness to a processor access. But, for example, in a television system, drawing and display delay of an EPG (Electronic Program Guide) and a data broadcast occurs, and this can cause users using the system to be stressed.
Therefore, efforts to improve responsiveness to the processor access are often made, while giving priority to an access from the real time master usually.
For example, Patent Document 1 discloses a technology to improve responsiveness to an access request of a processor in this kind of system.
According to the Patent Document 1, in the case where the real time master obtains a constant rate, and memory access requests of other masters are not targets of arbitration (the case where there are extra resources with respect to the access to a shared memory), an access from the real time master at a rate equal to or higher than the constant rate is allowed. This causes the real time master to access the shared memory more excessively than originally expected, which means that a margin is created with respect to the access which should be executed periodically. Accordingly, when a processor makes an access request, it is possible to allow the processor to access a shared memory using rates which was originally allocated to the real time master. Such a technology to improve responsiveness to a processor access in the situation where there is a margin, that is, the real time master executes an access at a rate equal to or higher than a constant rate is disclosed.    Patent Document 1: PCT International Publication No. WO 07/004,696 pamphlet